The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device that is designed to reduce the contact area between a heater and a phase change layer and a method for manufacturing the same.
In general, memory devices are generally divided into volatile RAMs (random access memory) which loses inputted information when power is interrupted and into non-volatile ROMs (read-only memory) which can maintain the stored state of inputted information even when power is interrupted. As to volatile RAMs, DRAMs (dynamic RAM) and SRAMs (static RAM) are well known. As the non-volatile ROMs, flash memory device such as an EEPROMs (electrically erasable and programmable ROM) are also well known.
While the DRAMs are excellent memory devices, DRAMs require high charge storing capacity. Accordingly, for DRAMs the surface area of the electrodes must be increased, which makes it difficult to accomplish a high level of integration. Due to the fact that two gates are stacked on top of each other for flash memory devices, high operation voltages are required when compared to a power supply voltage. According for flash memory devices, a separate booster circuit is needed to generate a voltage necessary for write and delete operations, which makes it also difficult to accomplish a high level of integration.
Therefore, much interest has been expended in the development of alternative novel memory device. These alternate novel memory devices are preferred to have simple configurations and preferred to be capable of accomplishing a high level of integration while retaining many of the desirable characteristics of non-volatile memory devices. As one example, an alternate novel memory device is the phase change memory device.
Phase change memory devices function on the basis of the fact that a phase change can occur in a phase change layer interposed between a bottom electrode and a top electrode. This phase change is associated with a reversible transformation between a crystalline state and an amorphous state brought about by a current flowing between the bottom electrode and the top electrode. Accordingly, information can be stored in a memory cell of a phase change memory device by measuring the resistances because the specific resistances between the crystalline state and the amorphous state are different.
Phase change memory devices often incorporate a chalcogenide layer composed of such material such as germanium (Ge), stibium (Sb), sulfur (S), selenium (Se) and tellurium (Te) as a phase change layer. As a current is applied, the phase change layer undergoes a phase change transition induced by heat, that is, Joule heat, between the amorphous state and the crystalline state. Accordingly, in the phase change memory device the specific resistance of the phase change layer in the amorphous state is often times higher than the specific resistance of the phase change layer in the crystalline state. In a read mode, by sensing the current flowing through the phase change layer, it can be determined whether or not the information stored in a phase change cell has a logic value corresponding to a ‘1’ or a ‘0’.
In the phase change memory devices in order to ensure that phase changes occur in a relatively stable and consistent manner, programming currents should be minimized or at least decreased. Thus, in the conventional art, in order to decrease programming current, much interest has been associated with regards to reducing the contact area between the heaters serving as bottom electrodes and the phase change layer. That is, as the contact area between the heaters and the phase change layer is reduced, the current density at these contact surfaces of the heaters and the phase change layer increases. Accordingly, the current required for driving the phase change operations of the phase change layer can be decreased.
For example, in the conventional art, after defining contact holes to have a small diameter of less than 100 nm, the corresponding formed heaters from these diminutive contact holes can also have a diminutive size. Then, a phase change layer is formed in contact with the open upper ends of the heaters.
However using conventional fabrication techniques to form these diminutive heaters having diameters equal to or less than 100 nm, a problem often arises in that it becomes increasingly more difficult in fabricating sufficiently uniform sized heaters in these memory cell array. As a result, the distribution of the programming current required to drive the phase change operations of the phase change layers of associated with these diminutive heaters widens to unacceptable levels.
Therefore, using conventional fabrication techniques, the size of these diminutive heaters cannot be made sufficiently uniform by simply decreasing the size of the heaters because the resultant distribution of programming currents becomes unacceptably wide. Accordingly, since it is difficult to achieve a narrow distribution of programming current and to achieve a decrease in the programming current, a novel method is needed.